Bus precharge circuits have been known in the art for charging capacitive loads such as data or address buses. The basic function of a precharge circuit is to charge a data communication line to a preselected value in an attempt to save time in the transfer of data. Charging data lines takes a certain amount of time because of the RC time constant associated with charging up the capacitance of the line. To the extent this can be done by a precharge phase in between data cycles, time can be saved. A bit of data may then be introduced onto the line and the voltage value of the line will be selectively changed (or not) in order to represent the state of the bit of data.
In one precharging scheme, binary "zero" and "one" bits are represented on the data line by zero volts and some positive voltage, such as five volts, respectively. If a "zero" bit is transmitted using the data line, the voltage on the data line will be driven down to zero volts; otherwise, if a "one" bit is to be transmitted, the line is left at +5 volts. Each register connected to this line will typically have a switchpoint, or a voltage below which the register will sense and store one state, and above which the other state will be sensed and stored. According to the above conventional precharging scheme, the bus actually has to be precharged to a level higher than the switchpoint of the receiving register or receiver. An overshoot has to be designed into the precharging scheme which causes an additional time delay when transmitting a "zero" level.
Also, high-point precharge schemes are susceptible to noise problems. This is because the charge on the high impedance bus itself will be responsible for writing a register if a "one" bit is desired to be transmitted. Since the precharge voltage value is the same as the logic "one" value, and since the switchpoint of the receiver is often set near the precharge value in order to optimize speed, noise, as from coupled, adjacent bus wires, may cause a misreading of the data to be transferred.
Also, in conventional bus or line sensing precharging schemes, the rate of precharge is substantially linear as it approaches a level to which the line is to be precharged. This worsens the amount of precharge overshoot, and therefore causes the additional consumption of time when dropping the precharged line to a logic level not associated with the precharge value.
Midpoint precharge schemes are known in the art, such as the one shown by H. B. Bakoglu and J. D. Meindl in "CMOS Driver and Receiver Circuits for Reduced Interconnection Delays", International Symposium on VLSI Technology, Systems and Applications, pp. 171-175, Taipei, Taiwan, May 1985. Midpoint precharging schemes have the advantage of not having a logic level of the line associated with the precharge value. Therefore, there is no reliance on the precharge voltage as a data value, conferring noise immunity. Unfortunately, the Bakoglu scheme is not suitable for a bus line having multiple ports. The Bakoglu precharge circuit is built right into each data receiver, rather than according one precharge circuit per line with multiple receivers on them. Also, the Bakoglu precharge scheme uses two inverters for sensing, causing a total of four-gate delays before turn off.
U.S. Pat. No. 4,763,023 issued to Spence shows a circuit precharge scheme in which a line can be precharged to a predetermined precharged value VPC. However, the Spence precharge circuit uses a P-channel pullup device with a linear precharge characteristic, thus, increasing precharge overshoot, and shows a precharging inverter that is connected to a line only through a gate, causing an additional gate delay.
In view of the foregoing, a need exists for a precharge circuit that produces no ringing or oscillation during precharge; has timing which is process independent; precharges the bus or line to exactly the switchpoint of the receiving device in order to maximize speed; operates well over a wide range of supply voltages; and has noise immunity.